********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Mar 17, 2014
*ECN S14-0475, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA66DP D G S 
M1 3 GX S S NMOS W= 7312500u L= 0.25u 
M2 S GX S D PMOS W= 7312500u L= 0.12u
R1 D 3 1.7398e-03 2.907e-03 2.028e-05 
CGS GX S 1.924e-09 
CGD GX D 1.000e-13 
RG G GY 1.45 
RTCV 100 S 1e6 0 0
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 7312500u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.9903e-05 NSUB = 1.12e+17 
+ KAPPA = 1.948e-02 NFS = 7.999e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.093e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 7.757e-08 TREF = 25 BV = 31 
+RS = 1.107e-02 N = 1.085e+00 IS = 6.878e-12 
+EG = 1.089e+00 XTI = 1.249e+00 TRS = 5.654e-04 
+CJO = 5.508e-10 VJ = 4.683e+00 M = 1.000e-00 ) 
.ENDS 